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NO.432—【獵頭職位：昆山需要一位 Analoglayout engineer】聯(lián)系人：Grace-Tai,郵箱：hr@kthr.com，微信也可查詢(xún)職位了！打開(kāi)手機(jī)微信，搜號(hào)碼“KTHR_COM”或查找微信公眾帳號(hào)“KT人才”或掃描以上二維碼即可添加，歡迎大家關(guān)注！ Responsibilities： 1. Full custom analog layout/verification and RCextraction. 2. Perform blocklevel layout. Conduct physical verification (DRC and LVS using Cadence tools). 3. Team work with analog designers, optimizelayout. Basic Qualifications: 1. Bachelor or above degreewith 3 years experiences in CMOS IC full-custom layout. 2. Experiences in Mixedsignal/analog/memory，etc. 3. Familiar with layoutskills and knowledge is must. 4. Goodteamwork/communication/positive is must. 5. Familiar with Cadence IClayout and verification tools 6. Having massive IP blockexperience 7. Familiar with ESD/Latchup/antenna and related layout solutions is a plus. 8. Familiar with rule deckis a plus. 福利：五險(xiǎn)一金、帶薪年假、公司股權(quán)激勵(lì)等，博士?jī)?yōu)秀人才可申請(qǐng)政府人才計(jì)劃補(bǔ)貼 |
